Senior FPGA IP Design engineer
Core
Plan, build, and execute end-to-end processing system solutions including Vivado IP configuration to software execution targeting customer use cases on AMD Xilinx products.
Role type
Senior IC FPGA IP Design Engineer
Builds
Processing IP solutions for AMD AECG FPGA/SoC/ACAP
Domain
Semiconductor / FPGA / SoC Design
Required skills
Verilog/SystemVerilog coding and simulation, FPGA timing constraints and STA, system-level architecture (AXI, PCIe, Ethernet), debugging systems on boards, Tcl/Python/Perl scripting
Preferred skills
C/Assembly programming, Xilinx SDX tools, GT Transceivers/SERDES understanding, boot and IO peripherals knowledge
Technologies
Vivado, Xilinx Simulator, ModelSim, NC-Verilog, VCS, AMD Xilinx/AECG FPGAs, AXI, PCIe, Ethernet, Tcl, Python, Perl, C, Assembly
Responsibilities
Define specification and implementation of processing system solution requirements, collaborate with cross-functional teams (marketing, architects, verification, firmware), drive requirements and deliverables with cross-site stakeholders, develop processing IP solutions for bare metal and OS hosted environments
Seniority
Senior, hands-on IC
