IP Verification Engineer
Core
Develop and maintain UVM-based verification frameworks, testbenches, and components for complex IP architectures (FPGA/ASIC) to ensure first-pass silicon success.
Role type
Senior IC IP Verification Engineer
Builds
Front-end design and integration of cutting-edge FPGA and ASICs
Domain
Semiconductor / Hardware Verification
Required skills
UVM, System Verilog, Verilog, Object Oriented programming, IP level verification, PCIe/CXL/NVMe/ethernet protocols, Python/Perl scripting, Computer Architecture knowledge
Preferred skills
Technical leadership, AI in verification automation, simulation profile/efficiency improvement, HLS tools/process
Technologies
UVM, System Verilog, Verilog, PCIe, CXL, NVMe, Ethernet, Python, Perl, HLS
Responsibilities
Collaborate with architects and hardware engineers to understand new features; Develop test plan documentation; Code IP or SS level UVM based testbenches and verification components; Build directed and random verification tests; Run regressions and debug test failures
Seniority
Senior, hands-on IC
