Sr. Systems Design Engineer - Data Center GPU
Core
Post-silicon validation and hardware debugging for Data Center GPU SoC-level IP blocks, focusing on system bring-up, error analysis, and root cause resolution.
Role type
Senior IC Systems Design Engineer (Hardware Validation/Debug)
Builds
Data Center GPUs and SoC-level IP blocks
Domain
Semiconductor / Hardware Engineering
Deliverable
production ML models
Required skills
Post-silicon validation, hardware debugging, SoC system architecture, board/platform-level debugging, C/C++/Python/Perl programming, scan dump analysis, JTAG tools, DMA/interrupt/memory subsystem knowledge, RAS concepts
Preferred skills
Multi-die/chiplet design experience, cache hierarchy management, software-hardware interaction knowledge, kernel-level driver familiarity, fault injection techniques
Technologies
JTAG, scan dump tools, DMA engines, interrupt controllers, memory subsystems, RAS mechanisms
Responsibilities
Execute post-silicon validation for SOC-level IP blocks including test plan development and coverage tracking; Debug hardware and system-level issues during bring-up and production phases; Perform post-silicon debug analysis using scan dump tools to investigate hangs and stalls; Triaging failures by correlating debug data across multiple IP domains; Develop and maintain validation test content for error handling and power management; Engage in hardware/software modeling to reproduce silicon failures
Seniority
Senior, hands-on IC
