Chip Level Defect Localization and Failure Analysis Engineer - RDSS Intern
Core
Perform electro-optical failure analysis (Photon-Emission, Laser-Voltage-Probing, Soft-Defect-Localization) to locate failing FETs or cells in advanced flip chip devices and support design-debug and yield-ramp.
Role type
IC failure analysis engineer (electro-optical)
Builds
Diagnostic data for physical root-cause identification and process technology improvement
Domain
Semiconductor manufacturing / Advanced CMOS technology
Required skills
Electro-optical failure analysis techniques, Scan-chain based logical test, Advantest 93k tester SW, CAD layout tools, Circuit simulation tools, Unix environment, Transistor physics, CMOS fabrication processes, SEM/TEM/FIB/AFM tools
Preferred skills
DFT for large-scale logical test, Test compression, Perl/TCL/C++/STYLE scripting
Technologies
Advantest 93k, PERL, TCL, C++, STYLE, SEM, TEM, FIB, AFM
Responsibilities
Setup test-loops within Advantest 93k tester SW, Use CAD layout tools for in-chip navigation, Run circuit simulation tools to aid analysis, Present and explain results to multi-functional teams, Support Die Probe Package second-source development
Seniority
Intern