Senior Silicon Validation Methodology Engineer - Low Power
Core
Own end-to-end low-power validation methodology from silicon to product for GPU, SoC, and CPU, defining test strategies, coverage bounds, and signoff criteria.
Role type
Senior IC silicon validation methodology engineer (low-power)
Builds
Reusable validation methodology, tools, metrics, and infrastructure for energy-efficient silicon products
Domain
Semiconductor hardware design and validation (low-power, power management)
Required skills
silicon validation methodology, low-power architecture design, power gating, DVFS, corner-case analysis, validation strategy, cross-functional consensus, AI-enabled analysis
Preferred skills
setting validation policy/playbooks, methodology reuse across multiple chips, expert debug of silicon LPWR issues, trade-off management (functionality vs. power, latency vs. coverage)
Technologies
GPU, SoC, CPU, AI tools for analysis
Responsibilities
Define test coverage bounds, PVT/variability, and signoff criteria; Invent new validation approaches beyond existing test plans; Drive cross-functional consensus on PPA and schedule priorities; Build automation and pre-silicon to post-silicon correlation workflows
Seniority
Senior, hands-on IC
