DPU Performance Validation Engineer
Core
Debug, analyze, and validate performance and functional behavior of NVIDIA silicon devices (DPUs) across single-die and multi-die systems in pre-silicon environments.
Role type
Senior IC DPU Performance Validation Engineer
Builds
NVIDIA DPU product lines
Domain
Semiconductor / Network Silicon Engineering
Deliverable
production ML models
Required skills
ASIC debug, RTL-level debug, waveform analysis, system-level performance root cause analysis, Python, C/C++, Linux environment
Preferred skills
Performance modeling, traffic generation, architecture studies, modern interconnects and protocols (PCIe, Ethernet, CHI), emulation platforms (Palladium, Veloce, FPGA prototyping)
Technologies
RTL, Linux, Python, C/C++, Palladium, Veloce, FPGA
Responsibilities
Debug and root-cause performance issues in pre-silicon environments; Collaborate with design, verification, architecture, and performance modeling teams; Develop and improve validation methodologies; Automate repetitive debug and validation tasks
Seniority
Mid-Senior, hands-on IC
