Senior ASIC Verification Engineer - HSIO
Core
Verify ASIC design, architecture, golden models, and micro-architecture of High Speed I/O controllers (e.g., Ethernet, NVLink) at IP/sub-system levels.
Role type
Senior IC ASIC verification engineer (HSIO)
Builds
High Speed I/O controllers for SOCs and GPUs
Domain
Semiconductors / High Speed I/O
Required skills
SystemVerilog, UVM, coverage-driven verification, random stimulus generation, assertion-based verification, debugging, analytical problem solving
Preferred skills
Perl, Python, SW programming languages, AI-enabled code assist tools, system-level architecture knowledge of HSIO designs (Ethernet, CXL)
Technologies
SystemVerilog, UVM, Ethernet, NVLink, CXL, Perl, Python
Responsibilities
Develop test plans, tests, and verification infrastructure; build reusable bus functional models, monitors, checkers, and scoreboards; collaborate with architects, designers, and pre/post silicon teams
Seniority
Senior, hands-on IC
