Senior Power and Performance Engineer
Core
Architect and integrate system-level performance and power management features, controllers, and policies to optimize product efficiency across datacenter and client products.
Role type
Senior IC power and performance engineer (silicon co-design)
Builds
Datacenter and client silicon products with optimized power-per-watt efficiency
Domain
Semiconductor hardware design and power management
Deliverable
production ML models
Required skills
DVFS, power gating, clock policy, sequencing, throttling, control systems, boot/reset, PVT dependencies, binning methodologies, VF characterization, HW/SW interaction, C/C++, Python, Perl, AI-driven optimization, machine learning algorithms
Preferred skills
Hands-on lab experience with oscilloscopes/multimeters/logic analyzers, silicon bringup exposure, modeling and simulation tools, open-source contributions, published research or patents
Technologies
C, C++, Python, Perl, AI tools, ML algorithms
Responsibilities
Build feature roadmaps for low-power and performance-per-watt needs; Partner with architecture, ASIC, board/platform, software/firmware, and marketing teams; Lead debug efforts and support bringup, validation, manufacturing, and customer escalations; Utilize AI to enhance performance prediction models and power management strategies; Implement AI-driven tools for automating data collection and analysis during validation and characterization phases
Seniority
Senior, hands-on IC
