CareerPlan

Senior Systems Prototyping and Emulation Engineer

US, CA, Santa ClaraFull-time$168k–$265k2026-10-06 → 2026-11-10
On-site

Core

Build FPGA prototypes and hardware emulation environments for next-generation GPUs, SOCs, NICs, and Switches to enable pre-silicon software development, validation, and performance analysis.

Role type

Senior Systems Prototyping and Emulation Engineer

Builds

FPGA prototypes and emulation platforms for DGX systems and high-performance SoCs

Domain

Hardware engineering, FPGA prototyping, hardware emulation, GPU/SOC design

Required skills

FPGA prototyping and hardware emulation architectures, RTL synthesis and place-and-route flows, Synopsys ProtoCompiler/Synplify Premier, Xilinx Vivado, Synopsys ZeBu/Siemens Veloce, Verilog/SystemVerilog, PCIe/CXL/NVLink protocols, C/C++ testbenches and transactors, DPI/PLI/SystemC interfaces, lab debug tools (oscilloscopes, logic analyzers)

Preferred skills

Scripting (Perl/shell/Tcl/Python), memory bring-up (LPDDR5/6, DDR5/6, CXL/PCIe), high-speed interfaces (USB4/3), pre-silicon software validation, firmware bring-up

Technologies

Synopsys ProtoCompiler, Synplify Premier, Xilinx Vivado, Synopsys ZeBu, Siemens Veloce, VCS, Verdi, GDB, PCIe, CXL, NVLINK, USB, CHI

Responsibilities

Build FPGA prototypes and hardware emulation environments by making RTL FPGA/emulation-friendly, partitioning the design, and taking it through synthesis, place-and-route, and emulator compilation flows; Improve performance of FPGA prototypes and emulation platforms, analyze timing/performance bottlenecks, and generate bitstreams/images; Bring up designs on FPGA prototyping and hardware emulation platforms and drive complex debug and problem-solving activities; Release prototypes and emulation environments to internal customers and support them through debug, validation, and software enablement; Understand the design and implementation, define configurations, develop/modify bring-up and testing infrastructure, and verify correctness of the design; Understand complex system topologies with multiple ASICs to realize DGX systems on prototyping platforms and emulators

Seniority

Senior, hands-on IC