Senior Power Analysis and Optimization Engineer
Core
Design and optimize energy efficiency for GPUs and SoCs using AI, LLMs, and advanced analytics to model power consumption and drive architectural improvements.
Role type
Senior IC power architecture and optimization engineer (AI/ML focus)
Builds
Next-generation GPUs and Tegra SoCs with optimized power profiles
Domain
Semiconductor hardware design (ASIC/GPU) and AI/ML for EDA
Deliverable
production ML models
Required skills
Power architecture, energy consumption modeling, low-power design, Verilog, ASIC design principles, Python, C++, Perl, machine learning, reinforcement learning, LLM development, data analytics
Preferred skills
Experience with PowerArtist, PrimePower, RTL Architect, building engineering copilots, cross-functional collaboration
Technologies
Python, C++, Perl, Verilog, PowerArtist, PrimePower, PrimePower RTL, RTL Architect, LLMs
Responsibilities
Analyze full-chip and unit-level power using RTL and gate-level tools; Develop and productionize power-aware ML/RL models for anomaly detection and dynamic power management; Design and train LLMs to interpret power data and recommend optimizations; Perform comparative power analysis across workloads and design options; Prototype architectural features in Verilog focusing on power implications; Automate power analysis flows and pipelines; Apply AI to automatically tune power-efficient configurations
Seniority
Senior, hands-on IC
