IP Post-Silicon Validation Lead
Core
Lead post-silicon validation, debugging, and system integration for AMD hardware IP (NBIO) across APU, CPU, and GPU SOC programs.
Role type
Senior IC IP Validation Design Lead
Builds
High-performance System-on-Chip (SoC) products for AMD's compute and graphics lines
Domain
Semiconductor / Hardware IP Validation / SoC Architecture
Required skills
SoC architecture, ASIC debug, digital design/verification, post-silicon validation, cross-functional collaboration, technical leadership, scripting (Python/Ruby), board/platform-level debug
Preferred skills
High-speed interface protocols, clock/power delivery analysis, PC architecture/PCIe knowledge, mentoring, automation development
Technologies
Logic analyzers, oscilloscopes, emulation frameworks, DV tools, Python, Ruby
Responsibilities
Define and execute functional test plans and validation strategies; debug IP issues across pre-silicon to production phases; collaborate with architects to resolve technical risks; drive tooling and automation innovation; support customer platform issues
Seniority
Senior, hands-on IC with leadership responsibilities
