IP Verification Lead with PCIe
Core
Plan, build, and execute verification plans for AMD's FPGA and ASIC IPs to ensure bug-free final designs.
Role type
Senior IC silicon verification engineer (ASIC/FPGA)
Builds
FPGA and ASIC IP designs
Domain
Semiconductor hardware design and verification
Required skills
UVM, SystemVerilog, Verilog, PCIe protocol knowledge, ASIC verification, testbench development, bug debugging, coverage convergence, Linux/Windows environments, scripting (Perl/Shell/Makefile)
Preferred skills
DMA verification, CXL protocol, AI/LLM usage in verification, HLS tools/process, leadership/mentorship
Technologies
UVM, SystemVerilog, Verilog, PCIe, CXL, DMA, Linux, Windows, Perl, Shell, Makefile
Responsibilities
Collaborate with architects and hardware engineers to understand product requirements; Develop UVM-based testbenches with directed and random test cases; Debug test failures and drive coverage convergence; Use AI to drive efficiency and automation; Provide silicon debug support to partner teams
Seniority
Senior, hands-on IC
