Sr. RTL Design Engineer – DDR/LPDDR Memory Controller
Core
Develop RTL designs for IP microarchitecture features within DDR/LPDDR memory controllers, optimizing for power, performance, and area.
Role type
Senior RTL Design Engineer (Memory Controller)
Builds
Memory controller IP for processors
Domain
Semiconductor / Computer Architecture
Required skills
RTL design, Verilog, SystemVerilog, Python, Perl, Tcl, Computer architecture, EDA tools, Lint, CDC, Timing analysis
Preferred skills
Digital logic design, DDR/LPDDR memory systems, Digital logic verification
Technologies
Verilog, SystemVerilog, Python, Perl, Tcl, EDA tools
Responsibilities
Define and implement IP microarchitecture features, Develop RTL designs for IP features, Analyze and optimize designs for power, performance, and area, Perform lint, CDC, and timing analysis, Collaborate with verification engineers to validate and debug IP
Seniority
Senior, hands-on IC
