RTL Design Engineer
Core
Design and verify block-level RTL IP and micro-processor subsystems for embedded security applications within System on Chip (SoC) products.
Role type
Senior IC RTL Design Engineer (Security IP)
Builds
Embedded micro-processor subsystems and hardware accelerators for SoC products
Domain
Semiconductor / Hardware Design / Security IP
Required skills
Verilog, System Verilog, C-DPI, RTL design methodology, ASIC design tools, bus/interface protocols (AXI, AHB, AMBA), FPGA emulation, scripting (Tcl, Ruby, Perl, Python)
Preferred skills
CPU/MP subsystem architecture knowledge, design for verification, technical leadership
Technologies
Verilog, System Verilog, C-DPI, Tcl, Ruby, Perl, Python, Makefile, ASIC tools, FPGA
Responsibilities
Develop and maintain block level RTL IP and micro-architecture; Debug RTL designs using C-DPI and verification testbenches; Triage regressions and analyze coverage; Participate in verification testbench specification; Debug integration issues with SoC teams; Provide technical leadership in design methodology.
Seniority
Senior, hands-on IC
