Signal Integrity Engineer - Serdes, Satellites (Starlink)
Core
Own signal integrity (SI) across the full lifecycle of Starlink satellite hardware, bridging electrical, mechanical, thermal, software, and RF domains to enable high-speed connectivity.
Role type
Senior IC Signal Integrity Engineer (Serdes, Satellites)
Builds
Starlink satellite payloads and high-speed communication systems
Domain
Aerospace / Satellite Communications / High-Speed Digital Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
3D EM simulation, high-speed digital channel simulation, SERDES architecture, high-bandwidth memory interface design, PCB layout, EMI/EMC debugging, Python/C++ programming
Preferred skills
Full lifecycle hardware development, cutting-edge DSP-based Serdes debugging, low-loss laminate expertise, high-volume PCB manufacturing knowledge, EMI/EMC de-sense resolution
Technologies
CST, HFSS, ADS, DDR4, LPDDR5, GPDDR6, QSPI NOR, eMMC, 56Gbps/112Gbps/224Gbps Serdes
Responsibilities
Specify, design, simulate, verify, qualify, and troubleshoot SI aspects of advanced satellite hardware; derive top-level specifications for PCB materials and channel subcomponents; design and optimize transition structures from die bump to die bump; root cause and fix issues in PCB manufacturing, PCBA test, or satellite integration; define best practices, simulation workflows, test methodologies, and signoff criteria
Seniority
Senior, hands-on IC