Senior FPGA & Firmware Engineer - SDR
Core
Senior FPGA engineer owning the realization of digital signal processing for a software-defined radio (SDR), taking algorithms from MATLAB/Simulink models through RTL synthesis to silicon on Zynq UltraScale+ MPSoC.
Role type
Senior IC FPGA & Firmware Engineer (SDR)
Builds
High-performance OFDM modems and mesh networking devices for Law Enforcement and Public Safety
Domain
Wireless communications, Digital Signal Processing, FPGA/RTL design
Deliverable
production ML models | product features
Required skills
VHDL/Verilog/SystemVerilog RTL design, Xilinx Vivado toolchain, MATLAB/Simulink modeling, Digital Signal Processing (DSP), Digital Communications (OFDM, MIMO, LDPC), Fixed-point arithmetic, On-chip interfaces (AXI4, DMA), RTL verification, Hardware bring-up and debug
Preferred skills
Master's/PhD in EE/Communications, HDL Coder experience, Zynq UltraScale+ MPSoC experience, RF transceiver integration (ADRV9001), GNU Radio familiarity, AI coding assistant usage
Technologies
Zynq UltraScale+ MPSoC, Xilinx Vivado, MATLAB/Simulink, HDL Coder, ADRV9001, GNU Radio, Git
Responsibilities
Research and implement SDR algorithms (OFDM, FFT, channel estimation); Generate RTL from Simulink and author custom VHDL/Verilog; Implement designs in Vivado with timing closure; Architect on-chip interfaces (AXI, DMA, CDC); Build verification suites (co-simulation, testbenches); Integrate modem with RF front-end and ARM cores; Debug radio hardware using oscilloscopes and logic analyzers; Mentor junior engineers
Seniority
Senior, hands-on IC
