CPU Formal Verification Engineer
Core
Drive and execute formal verification methodology for next-generation CPU IP design, ensuring industry-leading verification quality and productivity.
Role type
Senior IC formal verification engineer (CPU architecture)
Builds
CPU IP designs (datapath and control logic)
Domain
Semiconductor / Computer Architecture
Required skills
formal verification, proof by induction, COI reduction, abstraction, computer architecture, CPU pipelines, assertion IP (AIP), end-to-end properties, formal tools (JasperGold, VC Formal), infrastructure development
Preferred skills
debug skills for uArch functional failures, experience with FPV, FXP(x-prop), DPV, SEC
Technologies
JasperGold, VC Formal
Responsibilities
Architect and execute formal verification methodologies to cover CPU design; Scale formal verification to large, critical designs; Resolve convergence challenges using advanced techniques; Build and maintain formal verification infrastructure; Explore formalization of ISA and memory models; Foster technical relationships with EDA partners.
Seniority
Senior, hands-on IC
