AI芯片互联ESL建模工程师 - 芯片研发
Core
Designing and modeling interconnect architectures for AI chips to support high-performance inference and training scenarios.
Role type
AI chip interconnect architecture modeling engineer
Builds
AI chip interconnect architectures and microarchitectures for cloud and edge AI SoCs
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
C++, SystemC, performance modeling, RTL calibration, IP microarchitecture analysis, RDMA, Scale-up networking
Preferred skills
None stated
Technologies
C++, SystemC, RDMA, Scale-up networking
Responsibilities
Explore and model AI chip interconnect architectures; Analyze performance of interconnect architectures across different business scenarios; Test IP models, calibrate RTL, and optimize IP microarchitecture performance bottlenecks.
