端侧NPU性能建模工程师 - PICO
Core
Develop and maintain end-side NPU performance and power models covering core compute units, on-chip interconnect, multi-level memory architectures, and DMA mechanisms.
Role type
Senior IC NPU performance modeling engineer
Builds
Performance and power evaluation frameworks and tools for NPU architectures
Domain
Semiconductor hardware / NPU architecture / System-level modeling
Deliverable
production ML models
Required skills
C/C++, SystemC, computer architecture, memory subsystems, cache hierarchies, DMA controllers, tiling optimization, vectorization, systolic arrays, on-chip interconnect, CNN/Transformer analysis, operator fusion, memory reuse
Preferred skills
Machine learning accelerator modeling, fixed-point quantization, sparsity strategies, PyTorch, ONNX, TFLite
Responsibilities
Develop and maintain NPU performance/power models; Build evaluation systems and tools; Analyze performance bottlenecks using simulation data; Collaborate with algorithm teams on operator scheduling and fusion strategies; Output optimization recommendations to architecture teams
Seniority
Senior, hands-on IC
