阵列测试工程师（存算与AI） - 芯片研发
Core
Develop and optimize high-throughput electrical test programs for embedded memory arrays to characterize device consistency, stability, and failure sources in AI chip manufacturing.
Role type
Senior IC memory array test engineer
Builds
High-efficiency AI chips based on in-memory computing architecture
Domain
Semiconductor manufacturing / AI hardware
Deliverable
production ML models
Required skills
Embedded memory array testing, electrical parameter extraction, mismatch analysis, reliability testing (endurance, retention, disturb, drift, RTN), failure analysis correlation, test structure optimization, yield improvement
Preferred skills
Process variation analysis (systematic/random), PFA/EFA, DFM collaboration, trim/ECC strategy iteration
Technologies
Addressable Array, DMA test structures, WAT, Bitmap, CMP, etching, lithography, ion implantation
Responsibilities
Develop and optimize high-throughput electrical test programs for embedded memory arrays; Analyze full-array electrical distribution characteristics to identify mismatch root causes; Conduct stability and reliability testing including endurance, retention, disturb, drift, and RTN; Correlate electrical data with process issues using Bitmap and PFA/EFA; Drive test structure iteration and yield improvement through collaboration with PIE, DFM, and design teams
Seniority
Senior, hands-on IC
