芯片SLT测试工程师-芯片研发（上海）
Core
Design and execute System Level Test (SLT) plans for CPU and AI SoC chips, managing test environments and analyzing results to identify functional defects.
Role type
Senior IC chip SLT test engineer
Builds
Production-ready SoC chips (CPU, AI)
Domain
Semiconductor / Chip Design
Required skills
C/C++/Python/Java programming, SLT test case design, SoC chip architecture knowledge, interface testing (PCIe, DDR, JTAG, I2C, UART, SPI), test environment deployment, defect analysis
Preferred skills
FA support experience, mass production test flow knowledge
Technologies
C, C++, Python, Java, PCIe, DDR, JTAG, I2C, UART, SPI
Responsibilities
Design SLT test cases for functionality, performance, compatibility, and reliability; Debug and deploy SLT hardware/software environments; Analyze test results and track defect fixes; Support failure analysis (FA) for defective chips.
Seniority
Senior, hands-on IC
