CareerPlan

Senior Ingenieur Wafertest EWS Testchips (w/m/div)

Dresden, SN, deFull-time2026-10-27 → 2026-11-12

Core

Providing test and characterization solutions for SRAM and other test chips to enable rapid technology transfer and optimize reliability, quality, and yield.

Role type

Senior IC test engineer (wafer test)

Builds

Wafer test programs and test structures for test chips and test structures

Domain

Semiconductor manufacturing (wafer test)

Required skills

Wafer test or PCM experience, analog and digital circuit design knowledge, ASIC and MEMS technology understanding, test programming expertise, statistical analysis methods, Python or C/C++ scripting

Preferred skills

Experience in reliability, quality, and yield optimization

Technologies

SRAM, ASIC, MEMS, Python, C/C++