Chief Engineer & Architect, MRAM
Core
Senior technical individual contributor owning end-to-end product architecture for MRAM and memory subsystems from concept through silicon qualification.
Role type
Senior IC Chief Engineer & Architect (Memory Design)
Builds
Multi-generation memory products (MRAM, DRAM, NAND/NOR, SRAM, emerging NVM) for hyperscale data centers, cloud platforms, and enterprise infrastructure.
Domain
Semiconductor / Memory / Mixed-Signal IC Design
Required skills
Memory subsystem architecture, Floorplan and physical architecture, Multi-generation roadmap planning, Cross-functional trade-offs (process integration, circuits, DFT, packaging), Design methodology and EDA/CAD strategy, Mentorship, Executive and partner representation
Preferred skills
Embedded memory IP integration, Foundry engagement on PDKs, Emerging NVM architecture, Standards and patents
Technologies
Cadence, Synopsys, FinFET, CMOS, DTCO, JEDEC
Responsibilities
Define memory subsystem architecture and design specs, Drive floorplan and physical architecture decisions, Own the multi-generation roadmap and scaling, Decide cross-functional trade-offs across process and packaging, Own design methodology and EDA/CAD strategy, Mentor senior and principal engineers, Represent architecture to executives and partners
Seniority
Principal, hands-on IC
