Senior System Level Verification Engineer
Core
Lead design verification for complex ARM-based SoC hardware, focusing on system-level test environments, debugging, and ROM/Firmware bringup for Smart Edge SoCs.
Role type
Senior System Level Verification Engineer (Design Verification Team Lead)
Builds
Simulation and emulation test environments, test plans, and system-level test cases for SoC ASICs.
Domain
Semiconductor / Hardware Verification / SoC Design
Required skills
System level verification, C programming, RTL debugging, test planning, device modeling (JTAG, UART, SPI, I2C), waveform analysis, scripting (Python, Perl, Shell, Make), root cause analysis, OS boot debugging.
Preferred skills
Emulation/FPGA/post-silicon validation, complex IP interface validation (USB, Ethernet, PCIe, DDR), AI tools for test planning, SPDM/PLDM/MCTP protocols, Caliptra/Crypto/security APIs, bootloader/firmware development, firmware authentication.
Technologies
ARM, C, Python, Perl, Shell, Make, JTAG, UART, SPI, I2C, Confluence, Jira, Caliptra, SPDM, PLDM, MCTP.
Responsibilities
Develop SOC system level test environment for simulation and emulation; Develop testplan and tests including error and stress tests; Run and debug tests in regressions; Work with other teams in root-causing HW issues; Validation ROM; Work with SW team in debugging device driver issues and OS boots.
Seniority
Senior, hands-on IC with team lead responsibilities
