Senior Ingenieur Wafertest EWS Testchips (w/m/div)
Core
Responsible for providing test and characterization solutions for SRAM and other test chips to enable rapid technology transfer and optimize reliability, quality, and yield.
Role type
Senior IC test engineer (wafer test & characterization)
Builds
Wafer test programs and test structures for test chips and test structures
Domain
Semiconductor manufacturing (SRAM, ASIC, MEMS)
Required skills
Wafer test or PCM experience, analog and digital circuit design knowledge, ASIC and MEMS technology understanding, test programming expertise, statistical analysis methods, Python or C/C++ scripting
Preferred skills
Experience in reliability and quality optimization, complex test hardware knowledge
Technologies
Python, C/C++, SRAM, ASIC, MEMS
Responsibilities
Develop or modify test programs for technology and reliability characterization, analyze test failures electrically to identify root causes, determine suitable test conditions for fault localization, drive optimization of technology, test programs, or design, serve as the contact person for series production on reliability and yield projects
Seniority
Senior, hands-on IC
