ASIC Layout Engineer (m/f/d) - A OT AESS
Core
Generate block and chip layouts based on analog circuits/schematics to achieve robust DRC-compliant designs with efficient area utilization.
Role type
ASIC Layout Engineer (Analog)
Builds
Analog block and top-level layouts for semiconductor chips
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog circuit layout, Floor planning, Pin placement, Parasitic extraction, DRC/LVS verification, Tape-out support, Deep sub-micron effects knowledge (parasitics, coupling, matching), BCD technology experience (65-180nm)
Preferred skills
Analog circuit design understanding
Technologies
Layout tools (design, DRC, LVS, Extraction), BCD technology (65-180nm)
Responsibilities
Creating and integrating analog layouts on block and top level, Floor planning and pin placement, Parasitic extraction, Supporting design engineers to meet speed, area, power, DFM & ESD/EMV requirements, DRC/LVS & Tape out support
Seniority
Mid-level IC Engineer
