Senior ASIC AMS Verification Engineer (m/f/d) - A OT AESS
Core
Develop mixed-signal verification strategies, models, and test benches for automotive ASICs to ensure compliance with stringent automotive requirements.
Role type
Senior IC analog/mixed-signal verification engineer
Builds
Verification environments and test benches for automotive semiconductor applications
Domain
Automotive electronics and semiconductor design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Mixed-signal verification strategy, Verilog/Verilog-A/SystemVerilog, analog circuit design understanding, testbench development, verification automation scripting, post-silicon validation, functional requirement analysis
Preferred skills
Perl/Python/Makefile/Shell scripting, Cadence AMS Simulation environment, chip-level verification best practices
Technologies
Verilog, Verilog-A, SystemVerilog, Perl, Python, Makefile, Shell, Cadence AMS
Responsibilities
Develop mixed-signal verification strategy and test benches, create models for analog blocks, build block and system-level verification environments, construct support utilities for verification automation, mentor the team on modeling and verification, contribute to verification infrastructure development, formulate test plans based on functional requirements, execute self-checking tests, support post-silicon validation in the lab
Seniority
Senior, hands-on IC