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Technologist, RFIC Design Engineer

San Jose, CA, us💼 Full-time🗓 2026-07-09 → 2026-07-31

Core

Design of high performance RF and analog circuit blocks including transistor, block, and module level architecture, simulation, and layout verification.

Role type

Senior IC RFIC Design Engineer

Builds

RF and analog integrated circuits for mass production

Domain

Semiconductor manufacturing, RF/analog circuit design

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

RF and analog integrated circuit design, full CMOS circuit design (amplifiers, mixers, converters, drivers, receivers, CDR, equalizers, PA), 40nm and below CMOS technology, EDA tools (Cadence, Mentor, Siemens, Ansys), RF/analog block layout (LNA, mixer, ADC, DAC), floor planning, block and top level chip routing, high performance analog layout considerations (matching, EM-IR, SOA)

Preferred skills

Distributed design team experience

Technologies

Cadence, Mentor, Siemens, Ansys

Responsibilities

Design transistor level, block level and module level circuit architecture; perform simulation, optimization, and layout verification; prepare test plans; conduct reliability and yield assessment; correlate simulation to bench and bench to test; perform bench evaluation at silicon and application levels; document designs.

Seniority

Senior, hands-on IC

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