DDR Interface Evaluation Leader
Core
Lead technical execution of DDR interface evaluation for automotive SoCs (R-Car series) to ensure system stability and performance through silicon-level testing and margin analysis.
Role type
Senior IC hardware engineer (DDR interface evaluation)
Builds
Automotive SoCs (R-Car series) with high-speed memory interfaces
Domain
Automotive electronics / Semiconductor design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DDR interface evaluation, margin analysis, stress testing, root-cause analysis, analog behavior knowledge (PHY, PLL, jitter, noise, SI/PI, power integrity), technical leadership, cross-functional collaboration
Preferred skills
Board-level DDR interface evaluation, signal/timing/power measurement with lab equipment, external IP vendor coordination, automotive SoC project experience
Technologies
LPDDR4/4X/5/5X/6, DDR PHY, memory controllers, oscilloscopes, logic analyzers
Responsibilities
Lead technical execution of DDR interface evaluation, drive silicon and board-level evaluation and stress testing, define evaluation strategy and consolidate results, perform root-cause analysis for issues, provide technical leadership to global teams
Seniority
Senior, hands-on IC
