Principal RTL Design Engineer
Core
Own the microarchitecture and RTL for a major block or subsystem of the Reconfigurable Dataflow Unit (RDU) AI accelerator, from specification through tape-out.
Role type
Principal RTL Design Engineer (ASIC)
Builds
Compute datapath, on-chip network, and memory subsystems for the SambaNova Suite generative AI platform
Domain
Semiconductor / AI Hardware Acceleration
Deliverable
production ML models
Required skills
Synthesizable SystemVerilog, high-frequency datapath pipelining, static timing analysis, clock domain crossing, Python scripting, technical leadership
Preferred skills
RDU domain depth (compute, interconnect, memory), industry-standard interconnects (AXI, PCIe, HBM), formal property checking, advanced TSMC nodes, AI workload acceleration techniques
Technologies
SystemVerilog, Python, SambaNova RDU, TSMC nodes
Responsibilities
Write and debug synthesizable SystemVerilog RTL through full chip implementation; Own PPA trade-offs hitting aggressive frequency targets; Drive timing closure and design quality (synthesis, STA, lint, CDC, LEC); Partner with verification to define coverage and support debug; Drive AI and automation into the design flow; Mentor design engineers
Seniority
Principal, hands-on IC with mentorship
