Staff Engineer Mixed Signal Layout (f/m/div.)
Core
Execute full-custom IC and block-level layout from schematic to tape-out for high-frequency RF blocks and high-speed SerDes components, ensuring signal and power integrity.
Role type
Staff Engineer Mixed Signal Layout
Builds
High-frequency RF ICs and high-speed SerDes components
Domain
Semiconductor / Analog & RF Design
Required skills
Full-custom layout, CMOS and FinFET technologies, RF IC layout, high-speed interfaces (PCIe, Ethernet, USB, SerDes), DRC/LVS/ERC verification, Parasitic extraction and management, Floorplanning, EDA tools (Cadence Virtuoso, Siemens Calibre), Technical leadership, Mentorship
Preferred skills
None stated
Technologies
Cadence Virtuoso, Siemens Calibre
Responsibilities
Execute full-custom IC and block-level layout from schematic to tape-out for high-frequency RF blocks and high-speed SerDes components; Implement precise matching techniques and isolation strategies to prevent noise coupling; Run and debug full-chip physical verifications including DRC, LVS, ERC, and Antenna rule checks; Analyze and minimize parasitic resistance, capacitance, and inductance; Perform floorplanning, pad-ring assembly, and final chip integration considering ESD, latch-up, and electro-migration guidelines; Provide technical leadership and mentor junior layout engineers.
Seniority
Staff, hands-on IC with leadership