Engineer / Senior Engineer Digital Design
Core
Design and verify digital circuits for sensor and mixed-signal IPs, ensuring high-performance and low-power implementation.
Role type
Digital Design Engineer (RTL)
Builds
Sensor and mixed-signal IP blocks
Domain
Semiconductor / Digital IC Design
Required skills
RTL design coding, Logic Synthesis, Static Timing Analysis, LEC, Spyglass linting, CDC/RDC, DFT, ATPG, Power analysis, System Verilog, Verilog, VHDL
Preferred skills
Mixed-signal IP knowledge (ADC, PMU, oscillator, temperature sensors), Chip integration, Testability
Technologies
Cadence, Synopsys, System Verilog, Verilog, VHDL, LEC, Spyglass, Primetime
Responsibilities
Register Transfer Level (RTL) design coding and verify digital circuits, Perform RTL design and behavioral model coding, Execute DFT/power integrity related activities, Work with Physical designer to achieve timing closure, Support verification engineers to define test items, Support view generation engineers to verify IP views
Seniority
Junior to Mid-level (0-3 years experience)
