Staff / Senior Staff Engineer Digital Design (RTL Design)
Core
Architect and design high-performance, low-power digital circuits and mixed-signal IPs for sensors, defining specifications, RTL, and verification concepts.
Role type
Staff / Senior Staff Engineer Digital Design (RTL Design)
Builds
Sensor and mixed-signal IP blocks
Domain
Semiconductor / Hardware Design
Required skills
RTL design, Logic Synthesis, Static Timing Analysis, DFT, Power Integrity analysis, Behavioral modeling, Linting, CDC/RDC checks, Architecture definition, IP specification
Preferred skills
Experience with sensor IPs, Roadmap formulation, View generation support
Technologies
Cadence, Synopsys, Spyglass, LEC
Responsibilities
Define IP specifications and architecture with system engineers; Specify, RTL design and verify digital circuits for sensor IPs; Perform Logic Synthesis, Static Timing Analysis, and structural checks; Execute DFT and power integrity activities; Collaborate with physical designers for timing closure; Conduct design reviews and documentation; Support verification engineers in defining test items; Support roadmap formulation for sensor IPs; Assist view generation engineers in IP verification.
Seniority
Senior, hands-on IC
