Working Student / Internship – RTL Design & SPICE Simulation Automation (f/m/div)
Core
Develop expandable RTL in Verilog/VHDL, create simulation test structures, and build automated SPICE simulation flows for chip experiments.
Role type
Working Student / Intern RTL Design & SPICE Automation
Builds
Simulation-ready test structures, automated SPICE flows, reproducible reports/artifacts
Domain
Semiconductor / Hardware Design
Required skills
Verilog, VHDL, SPICE simulation, Python, Tcl, Linux command line, Git, digital design fundamentals (FSM, timing), CMOS circuit basics
Preferred skills
Bachelor's or Master's in Electrical Engineering
Technologies
Verilog, VHDL, SPICE, Python, Tcl, Linux, Git
Responsibilities
Develop parameterizable RTL for experiments, create and maintain simulation test structures, set up and execute SPICE analyses, build automated SPICE simulation flows with scripting, document workflows clearly, write supporting scripts for tool integration and automation
Seniority
Student / Intern
