Principal Engineer Design
Core
Design Lead for Power Management ICs and POL ICs, defining architecture, resourcing, and schedule while mentoring designers.
Role type
Principal Engineer Design (Analog/Mixed-Signal IC)
Builds
Power Management ICs and POL ICs for power systems and IoT
Domain
Semiconductor / Power Electronics / Analog & Mixed-Signal Design
Required skills
Analog & mixed-signal design, Power Management ICs, LDMOS/BCD process technologies, Cadence Virtuoso, EDA tools, Transistor-level design, DFT strategy, Production test development, Architecture definition, Circuit design, Debug, Documentation, Silicon evaluation and validation
Preferred skills
Power electronics knowledge, Modulator architectures, Team lead and manager experience
Technologies
Cadence tools, Virtuoso Custom IC Environment, CMOS/BCD technology
Responsibilities
Define feature set, chip architecture, resourcing, schedule and cost; Mentor less experienced designers; Support DFT strategy and implementation; Support production test development and ramp; Specification and transistor-level design of low-power/high-performance analog circuits; Perform all aspects of IC analog/mixed signal design from definition to production
Seniority
Principal, hands-on IC design with mentorship
