STAGE – Caractérisation et amélioration de la variabilité du procédé Back End en 18nm – F/H
Core
Study process variability in the Back End of Line (BEOL) for 18nm ePCM technology by performing intensive dimensional measurements, TEM analysis, and electrical response characterization.
Role type
Intern, Process Integration Engineer (Semiconductor Manufacturing)
Builds
18nm ePCM interconnection technology for non-volatile memory
Domain
Semiconductor manufacturing, 18nm node, Back End of Line (BEOL)
Required skills
Semiconductor device physics, Materials physics, Microelectronics process knowledge, Statistical analysis, TEM (Transmission Electron Microscopy) analysis, Electrical characterization (PT/EWS)
Preferred skills
Microelectronics design, Mask technology, Microsoft Excel
Technologies
TEM, PT/EWS, Microsoft Excel
Responsibilities
Perform intensive dimensional and thickness measurements on key BEOL fabrication parameters, Conduct TEM analysis to correlate with in-process measurements, Define a dashboard for key technology parameters, Study electrical responses based on variations of key parameters, Compare performance against reference process internally and with partners