Silicon Front End CAD Engineer
Core
Build and optimize Ericsson's OneRun front-end EDA flow platform to accelerate ASIC/FPGA design verification and emulation for 5G/6G infrastructure.
Role type
Senior IC Silicon Front-End CAD Engineer
Builds
OneRun platform (Python-based flow orchestration, tool abstraction, emulation integration)
Domain
Semiconductor EDA / ASIC & FPGA Design / 5G/6G Infrastructure
Required skills
Python software engineering, front-end EDA flow development, Linux, Git, CI/CD, SystemVerilog, UVM, ASIC/SoC design flows, EDA tool integration (Xcelium, VCS, JasperGold, VC SpyGlass), performance optimization, AI/LLM application to engineering workflows
Preferred skills
Emulation platform experience (Siemens Veloce, Cadence Palladium), building vendor-agnostic EDA frameworks, measurable improvements in flow runtime/compute efficiency
Technologies
Python, PyTest, Jenkins, LSF, SystemVerilog, UVM, Xcelium, VCS, JasperGold, VC SpyGlass, Siemens Veloce, Cadence Palladium, Kiro, ChipAgents
Responsibilities
Extend OneRun architecture and APIs with clean Python code; script and integrate new pilot flows for production; enable emulation workflows within OneRun; optimize flow runtime, startup overhead, and resource usage; apply AI tools for spec-driven development and user support; automate regression testing and release qualification.
Seniority
Senior, hands-on IC
