Front End Design Verification Engineer
Core
Verify the fetch unit for a high-performance out-of-order RISC-V CPU core, ensuring the processor is fed correct instructions efficiently.
Role type
Senior IC design verification engineer (CPU front-end)
Builds
High-performance RISC-V CPU cores for AI, HPC, and high-performance computing workloads
Domain
Semiconductor / CPU Architecture / AI Infrastructure
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, constrained-random testing, assertions, functional coverage, testbench development, CPU architecture (pipelines, fetch/decode, branch prediction, speculative execution, out-of-order), RTL debugging, C/C++, Python
Preferred skills
Experience with complex digital designs (SoCs, ASICs), microarchitectural design knowledge
Technologies
SystemVerilog, UVM, C, C++, Python
Responsibilities
Develop verification strategies for the instruction fetch unit, create sophisticated tests, debug complex RTL and simulation failures, ensure correctness across workloads and corner cases
Seniority
Senior, hands-on IC
