Runset QA Engineer
Core
Execute physical verification runsets (DRC, LVS, illegal layer, TUC, fill, LU/IOGNAC, denall, tic, tapein merge, IPC) for Synopsys ICV, Siemens Calibre, and Cadence Pegasus on Intel chip-level databases to mimic virtual tape-in.
Role type
Senior IC physical verification engineer (runset QA)
Builds
Physical verification runsets and regression suites for chip tape-outs
Domain
Semiconductor manufacturing / Physical Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DRC/LVS flow expertise, physical verification experience, automation scripting (Tcl/Python/Perl), regression suite management, layout pattern development
Preferred skills
Intel flow/process node expertise, 7nm or lower process node experience, desire to grow in physical verification career
Technologies
Synopsys ICV, Siemens Calibre, Cadence Pegasus, CalibreDRV, Tcl, Python, Perl
Responsibilities
Execute physical verification runsets including DRC, LVS, illegal layer, TUC, fill, LU/IOGNAC, denall, tic, tapein merge, and IPC; Identify and triage discrepancies between runsets for review and final disposition; Debug DRC/LVS rule deck failures during regressions and document failures to the development team; Develop layout patterns to check every design rule in the redbook design manual and integrate them into the QA regression suite; Automate the central regression system and maintain/manage the test bench
Seniority
Senior, hands-on IC