Staff, RTL Engineer
Core
Designing and implementing RTL for complex digital subsystems, fabrics, debug/test subsystems, and SoC-level integrations for high-performance AI/ML accelerators and RISC-V CPUs.
Role type
Staff RTL Engineer (Microarchitecture & SoC Integration)
Builds
High-performance AI/ML accelerator chips and RISC-V CPU cores
Domain
Semiconductor hardware design, AI accelerators, RISC-V architecture
Deliverable
production ML models | product features
Required skills
RTL design (Verilog), microarchitecture development, complex ASIC/SoC/chiplet development, digital subsystem integration, pre/post-silicon debugging, PPA optimization, industry-standard protocols (AXI, AHB, APB, I3C, SPI), DFT/DFD methodologies
Preferred skills
Open-source hardware projects, scan test, MBIST, JTAG, SoC debug architectures, RISC-V CPU cores
Technologies
Verilog, AXI, AHB, APB, I3C, SPI, RISC-V
Responsibilities
Drive microarchitecture and RTL development for digital IPs; collaborate with architecture, verification, physical design, and silicon validation teams; solve challenging logic and system-level design problems; perform root-cause analysis and silicon bring-up; evaluate and optimize PPA tradeoffs.
Seniority
Staff, hands-on IC with strategic impact
