Network Engineer - ML Infrastructure (High-Speed Interconnects)
Core
Design, build, and optimize high-speed copper and optical interconnects for large-scale AI training and inference clusters.
Role type
Senior IC ML Infrastructure Engineer (High-Speed Interconnects)
Builds
High-bandwidth, low-latency network fabric for AI/ML clusters (100k+ GPU scale)
Domain
AI/ML Infrastructure, High-Speed Interconnects, Photonics, Signal Integrity
Deliverable
production ML models
Required skills
High-speed copper and optical interconnect design, PAM4 SerDes performance, optical link budget analysis, transceiver component expertise, system-level simulation, failure analysis, vendor due diligence, industry standards knowledge (OIF CMIS, IEEE)
Preferred skills
CPO technologies, VCSEL/microLED/THz radio-based solutions, SiPh design process, subcomponent supply chain knowledge
Technologies
ACC, AEC, CPC, FRO, LRO/TRO, LPO, AOC, CPO, DR4/8, FR4, 1.6T products, 200G+ SerDes, 448G SerDes, TFLN, ring resonators, multi-core/hollow-core fiber
Responsibilities
Design and productize high-speed connectivity solutions for AI clusters; Own vendor due diligence and onboarding for new 1.6T products; Investigate opportunities for LPO and LRO; Evaluate early co-packaged and near-packaged engines; Perform system-level simulation of end-to-end fabric performance; Drive failure analysis and root cause investigation; Collaborate with ML training teams to translate workload patterns into interconnect requirements; Contribute to internal tooling for interconnect health monitoring and automation.
Seniority
Senior, hands-on IC