PCIe Post-Silicon Validation Engineer
Core
Hands-on PCIe post-silicon validation, link bring-up, physical-layer debug, and root-cause analysis of link stability and training issues.
Role type
Senior IC PCIe post-silicon validation engineer
Builds
PCIe connectivity solutions for rack-scale AI infrastructure
Domain
Semiconductor hardware, high-speed interfaces, AI infrastructure
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
PCIe architecture and protocol, silicon validation, post-silicon debug, high-speed interface development, problem-solving, hardware/firmware/software boundary navigation, scripting/programming, Linux
Preferred skills
PCIe Gen4/Gen5/Gen6/Gen7, PCIe PHY/SerDes/equalization/lane margining/signal integrity, PCIe compliance and interoperability testing, debugging intermittent/marginal/thermal-sensitive/corner-case failures, PCIe switches, networking/accelerator platforms, AI/ML tools for engineering debug and automation
Technologies
PCIe analyzers, state traces, registers, logs, eye diagrams, signal-integrity measurements, Linux PCIe debug tools, Python
Responsibilities
Perform hands-on PCIe post-silicon validation; Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability; Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements; Drive complex issues from initial failure through root-cause analysis and final resolution; Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries; Validate PCIe functionality across different generations, platforms, configurations, and operating conditions; Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests; Develop automation to improve validation coverage, debug efficiency, and regression testing
Seniority
Senior, hands-on IC