Principal Silicon Validation Engineer, SerDes/PAM4
Core
Develop and execute electrical validation tests to quantify parametric device performance and margins for AI/ML connectivity products.
Role type
Principal Silicon Validation Engineer (SerDes/PAM4)
Builds
Post-Silicon validation plans, automated IC and board testing, and compliance reports for high-speed interfaces.
Domain
Semiconductor validation, AI infrastructure, high-speed connectivity (PCIe, Ethernet, CXL)
Deliverable
production ML models | product features | dashboards & analysis
Required skills
SoC debug and development, high-speed interface validation (PCIe5/6, PAM4, Ethernet), electrical compliance testing, PRBS testing, Python scripting, bench automation, high-speed lab equipment operation (BERT, Oscilloscope, VNA), signal integrity analysis
Preferred skills
PCIe/CXL compliance standards, channel loss budgeting, de-embedding, simulation tools (MATLAB, Keysight ADS, PLTS)
Responsibilities
Formulate comprehensive post-Silicon validation plans, automate testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, work with internal customers to quantify margins and ensure robustness
Seniority
Principal, hands-on IC
