Principal ATE Test Engineer
Core
Lead ATE Test solutions for complex mixed-signal silicon SoC products from design through high-volume production ramp.
Role type
Principal ATE Test Engineer
Builds
ATE test programs, hardware, and test strategies for high-speed SoC products
Domain
Semiconductor manufacturing / High-speed interface protocols
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ATE test strategy definition, high-speed mixed-signal SoC test program development, tester platform selection and ATE hardware design, high-speed load board design, ATE pattern optimization, DFT techniques (SCAN, MEMBIST, SerDes), control interfaces (I2C, I3C, SPI, MDIO, JTAG), production test of high-speed SerDes (16Gbps+), ATE programming and bring-up, bench-ATE correlation and debug, lab equipment operation (protocol analyzers, oscilloscopes), Teradyne or Advantest 93k ATE platform expertise, C/C++ or Python programming
Preferred skills
Data processing with high-level languages, external loopback at wafer sort, modern databases, RF testing on ATE platform
Technologies
PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, Teradyne 93k, Advantest 93k, C/C++, Python
Responsibilities
Develop and oversee SoC test strategy, interact with manufacturing partners, define and implement ATE programs, own the product from design to high volume production ramp, develop ATE hardware for wafer sort and final test, implement ATE patterns to optimize resources and minimize test time, develop DFT techniques for maximum defect and parametric coverage, perform silicon/ATE bring-up and debug
Seniority
Principal, hands-on IC with strategy ownership
