CareerPlan

Staff Datapath Design Engineer

San Jose, California, United States of AmericaFull-time$190k–$246k2026-10-26 → 2026-11-10

Core

Lead the design, analysis, and optimization of digital and analog circuits for new NAND memory products, ensuring outstanding performance, power, and area (PPA) optimization.

Role type

Staff IC datapath design engineer (memory)

Builds

High-speed Datapath circuits at the block level for NAND memory products

Domain

Semiconductor / Memory / Analog & Digital IC Design

Required skills

High-speed circuit performance optimization, Circuit simulation (System Verilog, hspice), Silicon data analysis, Circuit Reliability verification (Aging, Electromigration, self-heating), Layout review, STARRC extraction

Technologies

System Verilog, hspice, Spice simulators

Responsibilities

Define architecture and chip plans including placement and routing optimization, Model parasitics and supervise layout, Perform circuit simulations to validate functionality and performance, Collaborate with domain experts to review final design details, Contribute to the development of new product opportunities, Perform verification processes with modeling and simulation

Seniority

Staff, hands-on IC