Principal Engineer, ASIC Validation
Core
Principal Engineer leading ASIC validation on pre-silicon platforms using ZEBU emulation and Xilinx FPGA flows to debug SoC implementations.
Role type
Principal Engineer, ASIC Validation
Builds
Pre-silicon SoC deployments and validation plans for memory/storage subsystems (PCIe, LPDDR, ONFI)
Domain
Semiconductor / Memory and Storage / ASIC Design
Required skills
ZEBU emulation, Xilinx Ultrascale FPGA, Vivado Flow, Verilog RTL coding, SoC prototyping, PCIe/LPDDR/ONFI architecture, VCS simulation, Python/Perl/TCL scripting
Preferred skills
HAPS 100/200, Palladium, AI-enabled tools, industry standard interfaces (AXI, PCIE)
Technologies
ZEBU, Palladium, Xilinx Ultrascale FPGA, Vivado, VCS, PCIe, LPDDR, ONFI, HAPS
Responsibilities
Complete Xilinx FPGA Flow and Protocompiler Tool flow; own complete SOC deployment on ZEBU; collaborate with Design/SOC C/FW teams on validation plans; debug PCIe/LPDDR/ONFI subsystems; run SOC C based simulations and debug using VCS; write Verilog RTL when required; work with overseas teams for bring-up/debug.
Seniority
Principal, hands-on IC
