Pre/Post Silicon Validation Engineer with PMIC Expertise
Core
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power world class products, with a specific focus on validating Power Management Integrated Circuits (PMICs) from the SoC perspective.
Role type
Senior IC silicon validation engineer (PMIC/SoC)
Builds
SoC power delivery and power management infrastructure
Domain
Semiconductor / ASIC Design / Power Management
Required skills
PMIC internals (buck/SMPS regulators, LDOs, operating modes, protection mechanisms), SoC-PMIC interface protocols (SPMI, I2C, I3C), power sequencing and sleep/wake flows, rail and regulator validation (DVFS/AVS), lab tool debugging (oscilloscopes, logic analyzers, protocol analyzers), C and Python programming, ARM SoC architecture knowledge
Preferred skills
Pre-silicon validation (emulation/FPGA), random stress stimulus framework creation, concurrent rail transition testing
Technologies
SPMI, I2C, I3C, ARM SoC, DVFS, AVS, PWM, PFM, Lauterbach debuggers, Oscilloscopes, Logic Analyzers, Protocol Analyzers, Power Analyzers, Source Measure Units, DMMs, Electronic Loads, Current Probes
Responsibilities
Develop and execute validation plans and coverage leveraging PMIC expertise; Validate SoC-PMIC interface (SPMI/I2C/I3C) including arbitration and register access; Define and execute sleep/wake and power sequencing scenarios; Validate rail and regulator behavior (voltage scaling, mode switching, slew rates); Collaborate with cross-functional teams to validate power management subsystems; Measure and analyze power/performance characteristics of SoCs; Create random stress stimulus validation frameworks; Debug and root-cause silicon failures using lab tools and document issues
Seniority
Senior, hands-on IC
