SVE content integration & SKU functional validation engineer
Core
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power products; specifically bring up SVE convex infra and IST framework for VI content enablement in production.
Role type
Senior IC ASIC validation engineer (SoC silicon validation)
Builds
Qualcomm Snapdragon SoC silicon validation infrastructure and validation software content
Domain
Semiconductors / ASIC Design / SoC Validation
Required skills
C language, Assembly language, C-assembly interworking, Operating systems/RTOS/Linux kernel internals, JTAG based debuggers, Compilers/linkers, Processor architecture (Multicore/Multiprocessor/SMP/MTE/heterogenous cores), Software development life cycle
Preferred skills
SoC architecture paradigms (interconnects, power management), FPGA/emulation platform bring-up, ARM Cortex-A7/A8/x86/PowerPC CPU architecture, Weakly ordered memory model/pipelining, Multi-threaded application optimization, Top level ASIC design methodology
Technologies
C, Assembly, Linux, RTOS, JTAG, FPGA, Emulation platforms, ARM Cortex-A7, ARM Cortex-A8, x86, PowerPC
Responsibilities
Develop/port/enhance validation software content and bring up for IP validation teams; Own SoC frequent regression and execute end-to-end regression suite considering power and performance corner cases; Execute SOC validation releases on bench in lab and support SLT teams in Debug; Use silicon debug hooks to measure power/performance/coverage and other KPI metrics; Collaborate with Systems validation Lead/system content engineer to understand validation requirements.
Seniority
Senior, hands-on IC
