Emulation Performance Methodology & Debug Engineer
Core
Develop and support pre-silicon emulation platforms for SoC designs, focusing on build generation, hardware bring-up, and low-level debugging.
Role type
Emulation Performance Methodology & Debug Engineer
Builds
Pre-silicon SoC platforms and emulation builds
Domain
Semiconductor / SoC Design / FPGA Emulation
Required skills
Verilog, SystemVerilog, C programming, Python, TCL, FPGA timing closure, JTAG debugging, kernel debugging, SoC architecture (CPU/DSP/NoC/PMIC), digital circuit validation
Preferred skills
Emulation platform experience (Veloce, Palladium), cross-site collaboration, executive communication, power/performance analysis
Technologies
Xilinx FPGAs, Intel FPGAs, Veloce, Palladium, JTAG, SystemVerilog, Python, TCL
Responsibilities
Design and deploy global methodologies for emulation build generation and debug, bring up new FPGA emulation/prototyping hardware and software, debug low-level software and hardware issues, validate and debug digital circuits, collaborate with architects and verification engineers
Seniority
Mid-level, hands-on IC
