High-Bandwidth Memory (HBM) System Validation Lead (AI Accelerator Platform)
Core
Lead pre-silicon and post-silicon validation of next-generation stacked memory solutions (HBM) integrated with large-scale AI compute platforms, driving memory bring-up, performance characterization, stress validation, reliability analysis, and production readiness.
Role type
Senior IC memory system validation lead (AI accelerator platform)
Builds
High-bandwidth memory subsystems for AI accelerator platforms
Domain
Semiconductor / AI Hardware / Memory Systems
Deliverable
production ML models
Required skills
HBM technology, DDR technology, memory controller architecture, silicon bring-up, system-level debug, stress validation, reliability analysis, root cause analysis, validation strategy development, automation frameworks
Preferred skills
chiplet-based architectures, NoC infrastructure, cache hierarchy validation, AI workload characterization
Technologies
HBM, DDR, AI accelerators, Compute fabrics, NoC
Responsibilities
Own end-to-end HBM validation strategy from emulation through production silicon; Develop comprehensive validation plans covering memory initialization, training flows, power-state transitions, reliability testing, error recovery, and manufacturing diagnostics; Drive pre-silicon and first-silicon memory bring-up and root-cause analysis of failures; Validate interaction between HBM, AI accelerators, compute fabrics, cache hierarchy, and NoC infrastructure; Develop stress scenarios representing real-world AI workloads; Lead complex silicon debug efforts analyzing crashes, hangs, data corruption, and performance bottlenecks.
